Microelectronic field effect transistors are widely used in integrated circuits including microprocessors, logic devices, memory devices and other integrated circuits. As is well known to those having skill in the art, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) generally includes laterally spaced apart source and drain regions in a substrate, with a channel region therebetween, a gate insulating layer on the channel and a gate on the gate insulating layer opposite the channel.
Field effect transistor performance may be measured by the ratio of on current to off current. On current refers to the current flowing between the source region and the drain region when the transistor is in an on state. On current is also referred to as "saturation current". Off current is the current which flows between the source and drain regions when the transistor is in an off state. Off current is also referred to as "leakage current". It is desirable for a field effect transistor to have a large on current in order to increase switching speed. A small off current is also desirable, so that the transistor consumes low power and may be used with low voltages. Accordingly, it is desirable for the field effect transistor to have a large on/off current ratio, so that the on current is large and the off current is small. Unfortunately, it is difficult to control the off current or leakage current in a conventional field effect transistor. Moreover, well known "hot electron" effects also increase the off current.
In order to solve these and other problems, Lightly Doped Drain (LDD) structures and offset gate structures have been utilized in field effect transistors. A lightly doped drain transistor is described in U.S. Pat. No. 5,198,379 to Adan entitled "Method of Making a MOS Thin Film Transistor With Self-Aligned Asymmetrical Structure". An offset gate field effect transistor is described in U.S. Pat. No. 5,208,476 to Inoue entitled "Low Leakage Current Offset-Gate Thin Film Transistor Structure".
FIGS. 1A-1F are cross-sectional views of a conventional offset thin film field effect transistor during intermediate fabrication steps. Referring to FIG. 1A, a thin polycrystalline silicon (polysilicon) or amorphous silicon film 102 is formed on a substrate 101 such as a quartz, glass, sapphire or other substrate. A gate-insulating layer 103 such as silicon dioxide is formed on the thin silicon film 102. A gate 104 comprising doped polysilicon, metal or an electrically conductive thin film (ITO) is formed on the gate insulating layer 103. A photoresist layer 105 is formed on the gate electrode 104.
As shown in FIG. 1B, gate insulating film 103 is etched using the photoresist layer 105 and the gate electrode 104 as a mask. As shown in FIG. 1C, the photoresist 105 is removed.
As shown in FIG. 1D, a photoresist pattern 105 is then formed on both sidewalls of the gate electrode 104. The lateral thickness of the sidewalls 105 on the thin film 102 will correspond to the lateral thickness of offset regions which are formed in the thin film 102 as described in FIG. 1E.
As shown in FIG. 1E, ion implantation is performed to form the offset regions 101a and 101b, a source region 102b and a drain region 102a. As shown in FIG. 1F, photoresist sidewalls 105 are then removed.
Unfortunately, in the above fabrication method, the need to form a second photoresist layer in FIG. 1D may require an additional masking step. Moreover, the lengths of the offset regions 101a and 101b may be different, which may thereby cause an asymmetrical electrical characteristic in the field effect transistor.
FIGS. 2A-2D are cross-sectional views illustrating a conventional thin film structure which employs a lightly doped drain, during intermediate fabrication steps. In FIG. 2A, a thin polysilicon or amorphous silicon film 202 is formed on an insulating substrate 201 such as quartz, glass, sapphire or the like. A gate insulating film 203 such as a silicon dioxide film, is formed on the thin silicon film 202 opposite the substrate 201. A gate electrode, for example of metal, insulated thermal oxide or polysilicon, is patterned on gate insulating layer 203.
As shown in FIG. 2B, lightly doped source and drain regions 205 and 206 are formed in a self-aligned manner using the gate electrode as a mask. For example, ion implantation of donor and acceptor dopants may be used at a concentration of about 1.times.10.sup.14 cm.sup.-2. Then, as shown in FIG. 2C, an insulating layer is formed and anisotropically etched to form insulating sidewall spacers 207 on the sidewalls of the gate electrode 204. Source and drain regions 208 and 209 may then be formed, self-aligned to the gate electrode 204, by ion implanting donor or acceptor dopants at a concentration of about 1.times.10.sup.15 cm.sup.-2, using the gate electrode 204 and the sidewall spacers 207 as a mask. Accordingly, lightly doped source and drain regions 205 and 206 remain under the sidewall spacers 207.
As shown in FIG. 2D, source and drain electrodes 210 and 211 respectively are connected to the source and drain regions 208 and 209 respectively.
Unfortunately, the thin film transistor of FIGS. 2A-2D may require additional masking steps and additional ion implantation steps, thereby complicating the fabrication thereof. Accordingly, despite the advances of lightly doped drain and laterally offset transistors, there is still a need for field effect transistors, and especially thin film field effect transistors, which are capable of large on/off current ratios, and which do not require complicated fabrication steps.